Electrically erasable memory cells (e.g., EEPROM cells) store binary data in the form of charge accumulation on a floating gate. EEPROMs are able to change between binary states by transferring charge between the drain and the floating gate by way of electron tunneling. This tunneling allows EEPROMs to be electrically programmable, erasable, and readable by the selective application of potential across the control gate, the drain, and the source.
A typical prior art EEPROM cell is shown and described in U.S. Pat. No. 4,377,857 to Tickle. Such a prior art EEPROM cell is shown in FIG. 1. Cell 10 has source 12 and drain 14 regions formed in silicon substrate 16. Channel region 18 extends between source 12 and drain 14. Substrate 16 is of a conductivity type opposite to that of source 12 and drain 14. Field oxide 20 is provided to insulate cell 10 from adjacent cells (not shown). Gate oxide 22 insulates polycrystalline floating gate 26 from substrate 16 and channel 18. A very thin layer of tunnel oxide 24 insulates a portion of floating gate 26 from drain 14 and allows for the tunneling of electrons between floating gate 26 and drain 14. Insulating layer 28 insulates control gate 30 from floating gate 26. Cell 10 typically has a threshold voltage of approximately 1.5 volts when in its neutral state.
FIG. 2 shows a portion of a conventional memory array 32 having EEPROM cells such as cells 10 of FIG. 1 arranged in eight columns (for simplicity, not all eight columns are shown). The sources of cells 10 are connected to a voltage supply V.sub.ss which is typically set at ground potential. The drain of each cell 10 is connected to an associated one of bit lines BL.sub.1 -BL.sub.8 via select transistors Q.sub.1 -Q.sub.8, respectively. The gates of cells 10a-10h are connected to a control line 34 via control transistor Q.sub.9. The gates of select transistors Q.sub.1 -Q.sub.8 and control transistor Q.sub.9 are coupled to a word line WL.
Referring also to FIG. 1, binary data is represented in cells 10 by the presence or absence of charge stored on floating gate 26 (FIG. 1), where a charged state is indicative of a binary "1" and an uncharged state is indicative of a binary "0". To charge, or erase, one of such EEPROM cells, a high voltage (e.g., 15 V) is applied to control gate 30 while drain 14 is grounded. Electrons tunnel from drain 14 to floating gate 26, resulting in an accumulation of negative charge on floating gate 26. This charge accumulation increases cell 10's threshold voltage such that when a read voltage is applied to control gate 30, cell 10 will not conduct.
To discharge, or program, one of cells 10, control gate 30 is grounded while a high voltage (e.g., 13 V) is applied to drain 14. Electrons tunnel from floating gate 26 to drain 14, thereby discharging floating gate 26 and lowering the threshold voltage of cell 10 such that cell 10 will conduct when a read voltage is applied to control gate 30.
Data stored in cells 10 is read as follows. Word line WL is pulled to approximately 5 volts while bit lines BL.sub.1 -BL.sub.8 are held at approximately 1.5-1.7 volts. A read voltage of approximately 2.5 volts is then applied to control gate 30 of cells 10 via control line 34. Those cells 10 having an uncharged floating gate 26 will conduct while those cells 10 having a charged floating gate 26 will not conduct. Thus, the binary state of cells 10 may be determined by sensing current flow on bit lines BL.sub.1 -BL.sub.8.
Where the stored data is highly sensitive or confidential, internal access to cells 10 may be inhibited via security circuitry such that only authorized persons are able to read the contents of cell 10.
However, data stored in array 32 is susceptible to unauthorized external reading by charge detection and microprobing techniques. In a typical charge detection technique, array 32 is deprocessed to directly ascertain whether any charge is present on floating gate 26 of each cell 10. For instance, control gate 30 of each cell 10 can be removed using any suitable etchant, thereby allowing one to directly determine whether charge is present on floating gate 26 (using a charge detector or scanning device) of each cell 10 and, hence, to ascertain the binary state of each cell 10.
Second, array 32 may be deprocessed to remove all passivation layers such that word lines WL, control lines 34, and bit lines BL.sub.1 -BL.sub.8 of array 32 are exposed for microprobing. Using any conventional microprobe or equivalent, appropriate read voltages may then be applied to the respective word, control, and bit lines to access and determine the binary state of each cell 10 within array 32 via current sensing as discussed above. Conventional internal security circuitry does not preclude electrically reading the contents of array 32 in such a way.
Thus, in order to fully protect data stored in such a non-volatile memory array, both the array and the individual memory Cells contained therein should be protected against unauthorized external detection via microprobing and charge detection, respectively.